1. Field of the Invention
The present invention relates to test circuits and circuit test methods, and particularly to a built-in self-test circuit and a circuit test method which can identify exact time of failure occurrence at high clock frequency.
2. Description of Related Art
One of known test circuit for a system large-scale integrated circuit (LSI) is a built-in self-test (BIST) circuit, which is a test circuit incorporated into LSI. This configuration has the advantage of checking the operations when completing the circuit. Thus, test circuits with various techniques have been proposed.
For example, Japanese Unexamined Patent Application Publication No. 2003-36694 (Fujiwara et al.) describes a BIST circuit. In this technique, a test circuit includes a defect accumulation section and stores test result information output from the BIST circuit into the defect accumulation section, thereby allowing retrieval of the test result information as needed after performing the test.
Japanese Unexamined Patent Application Publication No. 2002-107412 (Nakamura) describes another technique. This technique does not accumulate comparison results but calculates and outputs OR. It allows, upon output of a failure result, identifying where the failure occurs by the clock cycle at that time.
However, the present invention has recognized that the above techniques have the following disadvantages. The technique taught by Fujiwara et al. requires a large capacity of memory in order to store test result information, which results in a high chip cost. If the memory capacity is small, the memory cannot store sufficient information and fails to determine where a test failure occurs. The technique taught by Nakamura imposes the restriction that the clock frequency of a test circuit has to be within the range of the clock frequency of a tester in order to observe all the clock cycles. It is thus necessary to increase the tester clock frequency if the clock frequency of the test circuit is high.
Further, most of prior BIST techniques only check the circuit good or bad and they do not identify exact time (clock cycle) of failure occurrence which is mandatory information for failure analysis.